Regviz

Espressif Systems /ESP32-S3 /WCL /Core_0_STATUSTABLE12

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as Core_0_STATUSTABLE12

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-S3/WCL/Core_0_STATUSTABLE12#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CORE_0_FROM_WORLD_12)CORE_0_FROM_WORLD_12 0CORE_0_FROM_ENTRY_12 0 (CORE_0_CURRENT_12)CORE_0_CURRENT_12

Description

Status register of world switch of entry 12

Fields

CORE_0_FROM_WORLD_12

This bit is used to confirm world before enter entry 12
CORE_0_FROM_ENTRY_12

This filed is used to confirm in which entry before enter entry 12
CORE_0_CURRENT_12

This bit is used to confirm whether the current state is in entry 12

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data